Magnetic core matrix switch



p 1965 N. G. VOGL, JR 3,208,044

MAGNETIC GORE MATRIX SWITCH Filed April 26, 1961 2 Sheets-Sheet 2 FIG. 2

FIG. 50

168 6h 16f 1m H United States Patent Office Patented Sept. 21, 1965 3,208,044 MAGNETIC CORE MATRIX SWITCH Norbert G. Vogl, Jr., Wappingers Falls, N.Y., assignor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Apr. 26, 1961, Ser. No. 105,797 11 Claims. (Cl. 340-466) This invention relates to coincident Current matrix switches and, more particularly, to improvements in means for reducing noise in the output windings of such a switch.

Switching devices capable of applying power to any of a plurality of loads find many uses in the electrical art. One example of such use is in the control of a magnetic core matrix memory of the type employed in modern data processing machines. Such memories generally include at least one plane provided with separate row drive windings, each inductively coupling a row of cores; and separate column drive windings, each inductively coupling a column of cores. More than one plane is generally employed to increase the storage capacity of the memory. Excitation of both the selected row drive winding and the selected column drive winding of a plane causes the core at the intersection of these windings to have its magnetic condition changed.

Selection of a row drive winding or a column drive winding in such a memory may be accomplished by a corresponding coincident current matrix switch. The memor'y-row-selecting switch and the memory-columnselecting switch are each arranged in a manner similar to the arrangement of one plane of the memory being controlled thereby. For example, the switch for controlling the row drive windings has a number of cores equal to the number of row drive windings in the memory. These cores may be thought of as being grouped in a plurality of rows and columns, there being a respectively corresponding row input or column input winding linking all the cores in the associated row or column of the switch. These windings will hereinafter be referred to as ROW INPUT WINDINGS and COLUMN INPUT WINDINGS respectively. A switch core (sometimes hereinafter referred to as a drive core) may have its magnetic condition changed only in response to the joint excitation of the ROW and COLUMN INPUT WIND- INGS which link it. Each core of this switch is also linked by an individual output winding which is connected in series with and terminated by a respectively corresponding one of the row drive windings of the memory.

COLUMN INPUT WINDINGS linking it, the appearance of a current on either of these input windings causes a certain amount of flux change in the core. Thus, in

I addition to the large flux change in the selected core of the switch, there are small flux changes in all the other cores of the groups linked by either of the selected input windings. These flux changes induce undesirable noise currents in the drive windings connected in series with the ouput windings of these half-selected cores, which in turn cause undesired flux changes in all the memory cores coupled by these drive windings. These flux changes induce noise currents in the memory sense windings, and, may, if large enough, cause stored information to be lost. This danger of information loss is particularly acute in memory cores at the intersection of such a noise-containing drive winding and an energized drive winding.

Therefore, some method of eliminating the eifects of these noise signals is desirable. One method of solving this problem is to provide two common lines for each ROW INPUT WINDING, and connect all the output windings of the cores linked by the related ROW INPUT WINDING in parallel between its respectively associated common lines. This circuit provides excellent noise cancellation in the output windings of the half-select cores in the same row as the selected core (e.g., the cores linked by the same ROW INPUT WINDING as the selected core). However, there has never been provided means which will at the same time eliminate the effect of noise currents induced in the output windings of the half-selected cores in the same column as the selected core (e.g., the cores linked by the same COLUMN IN- PUT WINDING as the selected core). Prior art circuits, therefore, solve only half of the problem.

It is therefore an object of this invention to provide means for further reducing noise in the output windings of matrix switches.

A more specific object of this invention is to provide means for cancelling the effect of half-select noise currents in both dimensions of matrix switches.

Another object of this invention is to provide means for cancelling the effect of all noise currents induced in the output windings of a coincident current matrix switch by flux changes in the half-selected cores of the switch.

The above objects are accomplished in the basic embodiment of this invention by providing circuit means for returning the output current through all the noise-containing output windings and in a sense opposite to the noise currents. This means includes a plurality of first common lines, one respectively associated with each of said rows of cores, and a plurality of second common lines, one respectively associated with each of said columns of cores. Each output winding is connected between its respectively associated common lines. The output windings are, therefore, connected in common in one dimension at the drive end of the windings and in another dimension at the load end of the windings.

A further object of this invention is to provide means for accomplishing the above-described noise cancellation with a minimum increase in the load faced by the selected switch core.

This object is accomplished by providing, in an improved embodiment of this invention, an impedance element in series with each of the common lines and connecting all of the common lines to a common point. The load faced by the selected switch core will be minimized if the impedance element is an inductor.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

In the drawings:

FIG. 1 is a simplified schematic diagram illustrating one embodiment of a coincident current matrix switch employing the basic concepts of this invention.

FIG. 2 is a modified schematic diagram of the output circuit for the switch shown in FIG. 1, the diagram being drawn to more clearly illustrate the current path under certain operating conditions.

FIG. 3 is a schematic diagram of an improved embodiment of the switch shown in FIG. 1.

FIG. 4 is a modified schematic diagram of the embodiment of the invention shown in FIG. 3, the modification being similar to that of FIG. 2.

FIGS. 5a and 5b are graphic representations of the output current from a fully-selected core and a halfselected core, respectively, drawn to a common time scale.

A first illustrative embodiment of this invention, shown in FIG. 1, consists of nine magnetic cores 10a- 10i arranged in thre horizontal rows of three cores each and into three vertical columns of three cores each. Although a nine-core square-matrix is shown in FIG. 1, it is to be understood that the size of the switch will depend on the size of the memory matrix or other load it is driving, and that any reasonable number of cores may be employed. It is also to be understood that, although the concept of the invention is illustrated with respect to a square matrix, it may also be applied to rectangular or otherwise arranged matrix switches.

All the cores in each horizontal group are linked by a common ROW INPUT WINDING 12x12z and all the cores in each vertical group are linked by a common COLUMN INPUT WINDING 14x-14z. Each drive core also has passing therethrough an output winding 1611-161 which terminates in a drive winding for a corresponding row or column of the core memory. These drive windings serve as the load for the drive-core output win-dings and are represented in FIG. 1 by inductorresistor combinations 18a-18i. While in FIG. 1 it appears that there is a plane of drive windings for each plane of the memory, this arrangement has been chosen primarily for convenience of illustration and other arrangements may be used. For example, where the individual bit positions of a data word are stored in the group of cores occupying corresponding positions in each of the planes, each drive winding will link all the memory cores located in a corresponding row (or column) of the memory. The output windings for each row of drive cores are connected togther at their core end by a common line 20x-20z; and the output windings for each column of drive cores are connected together at their load end by a common line 22x-22z.

The cores 10a-10i are of a well-known variety which are capable of existing in either of two saturation conditions. A current of a given polarity and a certain minimum magnitude flowing in a winding linking a core will induce flux changes in the core which will cause it to switch to one of its saturation conditions, if it is not already in that condition, and will have no effect on the core if it is in that saturation condition. An input sig nal of the opposite polarity will induce converse flux changes in the core. An input signal of less than the minimum magnitude necessary for switching will induce small reversible flux changes in the core, but on the termination of these signals the core will return to its pre- 'vious saturation condition. A flux change induced in a 'core will in turn induce a potential across the output winding linking the core, causing current to flow in this winding. When a core is switched, the output potential so induced will cause an output current I (FIG. a) which, except for rise and fall time, is of a constant, relatively high magnitude. FIG. 5b shows the relative duration and magnitude of the noise current I induced 'in the output winding of a core having a small flux change induced therein. The noise current has a duration which is approximately equal to the rise time of the output 7 current.

"these two windings will be switched from its first to its second saturation condition. But, the input current in winding 12x will also cause a small fiux change in cores 1 d and 10g, while the input current in winding 14x will cause a similar small flux change in cores 1% and 100. 'The switched core 10a will hereinafter be referred to as the fully-selected core" while the cores 10b, 10c, 10d

and 10g having small flux changes induced in them will hereinafter be referred to as the half-selected cores. The output current I, (FIG. 5a) induced in the selected output winding 16a is utilized to drive a row of cores in the memory array; however, the noise currents I (FIG. 5b) induced in the output windings 16b, 16c 16d and 16g perform no useful function and could as mentioned before, cause information loss in the memory array.

FIG. 1 has been redrawn as shown in FIG. 2 to more clearly illustrate how the noise currents are reduced to a harmless level my applying the concepts of this invention. As above, it is assumed that core 10a is the fullyselected core. Referring to FIG. 2, it is seen that the winding pattern of this invention provides a plurality of return paths for the output current I induced in the selected output win-ding 16a. All of these paths pass at least once through output windings 16b and in a direction opposite to that of the noise currents 1,, induced therein and many of the paths also pass through windings 16d and 16g in a direction opposite to that of the noise current induced therein.

The return paths are of many types. An example of the shortest possible type of path would be that including output winding 16a, common line 22x, output winding 16b, common line 20y, output winding 16h, common line 22z, output winding 16g, and common line 20x back to the output winding 16a. In tracing through this path, it can be seen that the direction of current flow of the output current I in the windings 16b and 16g would be opposite to the direction of flow of the noise currents I induced therein. The net current flowing in these windings will therefore be equal to I minus some fraction of I Another example of a path of this type would be that including output winding 16a, common line 22x, output winding 16c, common line 20z, output winding 16 common line 22y, output winding 16d, and common line 20x back to output winding 16a. Since the paths of this type are the shortest possible ones, it can be assumed that a large percentage of I will return through this sort of path. By applying Kirchoifs current law at each junction of the circuit, it can be seen that I will divide and recombine so that half of 1,, will be flowing in each of the half-selected output windings. This probably will result in return currents which not only cause the noise currents to be cancelled, but, in all likelihood, also result in a net backward current in the output windings of the half-selected cores. However, in a larger switch than that shown in FIGS. 1 or 2, the fraction by by which I would be multiplied would be something less than one-half and a more complete mutual cancellation would be obtained.

It should be noted that, with this arrangement, there is no current flow in any closed loop of the switch which does not contain the output winding 16a of the fullyselected core. Since all of the cores 10a-101' have substantially similar hysteresis curves, and, since all of the half-selected cores are energized by equal exciting currents, the potentials developed across the output windings of these half-selected cores will be substantially equal. Therefore, for example, the net potential around the closed loop including output winding 16b, common line 22x, output winding 160, common line 202, output winding 16 common line 22y, output winding 16c, and common line 20y would be equal to zero. Any other closed loop not containing the output Winding 16a of the selected core will also have a net potential of zero around it. No current can, therefore, flow in these loops.

It was assumed that the cores 10a-10i were initially in one of their saturation conditions. After the completion of the above-described cycle of operation, the

, switched core, 10a in the above example, is reswitohed to its initial condition by -a bias or other well-known'mean's. This return to the initial condition would cause noise currents (-1 to be induced in the output windings of the half-selected cores. These noise currents are reduced in the same manner as the noise currents I induced on the switching cycle except that all polarities are reversed.

While a very high degree of noise cancellation can be attained with the circuit arrangement shown in FIG. 1, this advantage is obtained at the expense of greatly increasing the load faced by the selected drive core 10a. As has been mentioned, the shortest return path for the output current passing through winding 16a is through three other output windings. Each of these extra output windings has a load 18in series with it. Since there are parallel paths for the output current 1 the load faced by the selected drive core is not increased by a factor of three times the impedance of a winding 16 and its load 18, but there is an appreciable increase in this load. Referring now to FIGS. a and 5b, the noise currents I are of relatively short duration compared to the output current 1 it, therefore, would be very desirable to cancel the noise currents while still providing a short-circuit return path for the output current once steady state conditions have been reached.

The above object is accomplished in the improved embodiment of the invention shown in FIG. 3. This circuit diflYers from that shown in FIG. 1 in that each of the common lines 20x-20z and 22x-22z is extended and an inductance element 24 is inserted in series therewith. Each of the common lines 20x20z is connected to a first common line 26 and each of the common lines 22x-22z is connected to a second common line 28. The common lines 26 and 28 are connected at a common point 30.

The operation of this embodiment of the invention will be described with reference to FIG. 4, this being a modified drawing of FIG. 3, drawn to more clearly show the current return paths, again taking core a as the fully-selected core. In this circuit, in addition to the current paths through the other switch windings mentioned in connection with FIG. 2, there is also, in parallel with these paths, a current return path fior I through common line 22x, inductor 24 in series therewith, common' line 28, common line 26, common line x and the inductor 24 in series therewith. If the inductors 24 each have a sufiiciently large inductance, a large percentage of the output current I will still flow through the output windings of the half-selected cores during transient conditions, causing noise cancellation in substantially the same manner as that achieved with the circuit of FIG. 2. However, once steady state conditions have been attained, the impedance of the inductors 24 will drop to nearly zero and the above-described path will supply nearly a short-circuit return path for the output current 1 Therefore, for a large portion of the operating cycle, the fullyselected core 10a is required to drive only its own load 18a.

For optimum noise cancellation, the inductors 24 should be selected to be of such a value that the potential drop induced across them by current I flowing through them will be substantially equal to one-half the potential induced across the output windings of the half-selected cores. If the inductors are of this value, the magnitude and the sense of the potential induced across an inductor 24 is the same as that induced across the output winding of a half-selected core, and the net potential around any closed loop not containing the output winding 16a of the fully-selected core will still be equal to zero. For example, the net potential around the closed loop including output winding 16g, common line 222, its series connected inductor 24, common line 28, common line 26, common line 20x and its series connected inductor 24 is equal to Zero; the potential-s across winding 16g and across the inductors in series with common lines 22z and 20x being equal and opposite. Similar equal and opposite potentials will be found in any other closed loop not containing output winding 16a. (It should be noted that, in a practical circuit, the waveform of the potential induced across an inductor 24 and that across the output winding of a half-selected core will not be identical, so

that, although the average magnitude of these potentials are equal, the instantaneous magnitudes will not always be the same. Some instantaneous current will therefore flow in the loops containing, inductors 24.)

The method of noise cancellation shown in FIG. 3 has been successfully used in a 10 x 10 matrix to reduce noise to the point where the ratio of the half-select core outputs to the full-select core outputs was less than 0.002.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without. departing from the spirit and scope of the invention.

I claim:

1. A matrix switch of the type comprising:

an array' of saturable magnetic cores;

a set of first input windings and a set of second input windings, there being a unique pair of said input windings, one for each. of said two sets, linking, each core of the array, whereby any individual core of said array can be selectively switched by applying suitable current impulses to the pair of input windings by which it is linked, while all of the other cores linked by the same input windings will have only small flux changes induced in them by said current impulses;

and a plurality of load-terminatedv output windings, one for each of said cores, each of said. output windings being: adapted to have: an output current induced therein in response to the switching of its associated core and a noise current induced therein in response to a small flux change in its associated core;

characterized by the provision of circuit means including said output windings connected in series parallel with each other for returning the output current through all the noise-containing output windings and in a sense opposite to said noise currents.

2. A switch of the type described in claim 1, further characterized by circuit means for shunting said. return circuit means, said shunt circuit means including means having a time limited high impedance condition of shorter duration than the output current.

3. A switch of the type described in claim. 2 wherein the duration of said high impedance condition is substantially equal to the duration of the noise current.

4. Amatrix switch having an array of saturable magnetic cores;

a set of row input windings and a set of column input windings, there being a unique pair of input windings, one from each of said sets, linking each core of the array; comprising:

a plurality of load-terminated output windings, one

for each of said cores;

a plurality of first common means, one for each of said row input windings, for electrically connecting a first end of each output winding of a core linked by the related row input Winding to the corresponding end of each other output winding so linked;

and a plurality of second common means, one for each of said column input windings, for electrically connecting the other end of each output winding of a core linked by the related column input winding to the corresponding end of each other output winding so linked.

5. A matrix switch having an array of saturable magnetic cores;

a set of row input windings and a set of column input windings, there being a unique pair of input windings, one from each of said sets, linking each core of the array; comprising:

a plurality of load-terminated output windings, one

for each of said cores;

a plurality of first common lines, one for each of said row input windings, each of said common lines having a first end of all the output windings of the cores linked by the related row input winding connected thereto; and

a plurality of second common lines, one for each of said column input windings, each of said second common lines havingthe other end of all the output windings of the cores linked by the related column input winding connected thereto.

6. In a circuit of the type described in claim 5, an impedance element connected in series with each common line of said first and second plurality of common lines, and means fior connecting all said common lines to a common point.

- 7. A circuit of the type described in claim 6 wherein said impedance elements are inductors.

8. A matrix switch of the type used to energize drive windings of a magnetic core matrix memory, the switch having an array of saturable magnetic cores;

a set of first input windings and a set of second input windings, there being a unique pair of input windings, one from each of said sets, linking each core of the array; comprising:

a plurality of output windings, one for each of said cores, each of said output windings being terminated by a drive winding for the core matrix memory;

a plurality of first common lines, one for each of said first input windings, each of said common lines having connected thereto the unterminated end of all the output windings of the cores linked by the related first input winding; and

a plurality of second common lines, one for each of said second input windings, each of said second common lines having connected thereto the drive windings terminating the output windings of the cores linked by the related second input winding.

9. A matrix switch comprising:

an array of saturable magnetic cores;

a first set of input windings and a second set of input windings, there being a unique pair of said input windings, one for each of said two sets, linking each core of said array, whereby the electrical impulsing of a first input winding, selected from said first set of windings, and a second input winding, selected from said second set of windings, causes one of said cores to switch; a first portion of the remaining cores of said array being linked by said first input winding, a second portion of the remaining cores of said array being linked by said second input winding, and a third portion being linked by neither said first nor said second input winding, the cores of said first and second portions having a small flux change induced therein when said first and second input windings are impulsed;

a plurality of load-terminated output windings, one for each of said cores, each of said output windings being adapted to have an output current induced therein in response to the switching of its associated core and a noise current induced therein in response to a small flux change in its associated core;

first return circuit means for carrying the output current induced in the output winding associated with said switched core to the noise-containing output windings associated with the cores linked by said first input winding, said output current being introduced into said last-mentioned output windings in a sense opposite to the noise currents induced therein;

second return circuit means for carrying the output current passing through said last-mentioned output windings to theou-tput windings associated with said cores not linked by either said first or said second input winding;

third return circuit means for carrying the output current passing through said last-mentioned output windings to the output windings associated with the cores linked by said second input winding, said output current being introduced into said last-mentioned output windings in a sense opposite to the noise currents induced therein; and

fourth return circuit means for carrying the output current passing through said last-mentioned output windings back to said output winding associated with said switched core.

10. A switch of the type described in claim 9 wherein said first return circuit means includes means for carrying an equal portion of the output current induced in the output winding associated with the switched core to each of the noise-containing output windings associated with the cores linked by said first input winding;

wherein said second return circuit means includes means for carrying an equal portion of the output current passing through said output windings associated with said cores linked by said first input winding to each of the output windings associated with the cores which are not linked by either said first or said second input winding; and

wherein said third return circuit means includes means for carrying an equal portion of the output current passing through said output windings associated wit-h said non-linked cores to each of the output windings associated with the cores linked by said second input winding.

11. A switch of the type described in claim 9, further characterized by circuit means for shunting said return circuit means, said shunt circuit means including means having a time limited high impedance condition of shorter duration that the output current.

References Cited by the Examiner UNITED STATES PATENTS 2,947,977 8/60 Bloch 340174 IRVING L. SRAGOW, Primary Examiner. 

4. A MATRIX SWITCH HAVING AN ARRAY OF SATURABLE MAGNETIC CORES; A SET OF ROW INPUT WINDINGS AND A SET OF COLUMN INPUT WINDINGS, THERE BEING A UNIQUE PAIR OF INPUT WINDINGS, ONE FROM EACH OF SAID SETS, LINKING EACH CORE OF THE ARRAY; COMPRISING: A PLURALITY OF LOAD-TERMINATED OUTPUT WINDINGS, ONE FOR EACH OF SAID CORES; A PLURALITY OF FIRST COMMON MEANS, ONE FOR EACH OF SAID ROW INPUT WINDINGS, FOR ELECTRICALLY CONNECTING A FIRST END OF EACH OUTPUT WINDING OF A CORE LINKED BY THE RELATED ROW INPUT WINDING TO THE CORRESPONDING END OF EACH OTHERE OUTPUT WINDING SO LINKED; AND A PLURALITY OF SECOND COMMON MEANS, ONE FOR EACH OF SAID COLUMN INPUT WINDINGS, FOR ELECTRICALLY CONNECTING THE OTHER END OF EACH OUTPT WINDING OF A CORE LINKED BY THE RELATED COLUMN INPUT WINDING TO THE CORRESPONDING END OF EACH OTHER OUTPUT WINDING SO LINKED. 